1. Technical Field of the Invention
The present invention relates generally to the field of wireless technology and, more particularly, to a method of and system for digital radio transceivers.
2. Description of Related Art
Wireless technologies such as, for example, terrestrial and satellite mobile communications and short-range wireless systems such as BLUETOOTH, often use M-ary differential encoded phase shift keying (MDPSK) for transmitting data. MDPSK is typically employed because of its advantageous characteristics, such as nonnecessity of carrier recovery circuits, fast acquisition performance, phase ambiguity resolution, and good performance over multipath fading channels.
A current solution for improving MDPSK detection performance utilizes a conventional differential detection circuit equipped with an infinite impulse response (IIR) filter combined with decision feedback. The carrier frequency offset typically generated in mobile communications is compensated for by a carrier frequency tracking loop. The semi-coherent demodulator approximates the performance of a coherent MDPSK demodulator without requiring carrier phase acquisition and tracking.
Referring now to FIG. 1, a known semi-coherent demodulator 100 is illustrated. In the FIGURES, the bold arrows indicate a complex signal and the thin arrow indicate a real signal. An input signal xi is received in complex form by the semi-coherent demodulator 100. The semi-coherent demodulator 100 manipulates the input signal xi into amplitude Ai100 and phase θi100 components of a real signal via a magnitude calculator 104 and a phase calculator 106, respectively, according to the following equation:xi=Ai100ejθi100 i=1,2,3  (1)To create a reference signal ui100, an impact of modulation on the input signal xi is removed from Equation 1. The impact of the modulation may be removed by rotating the input signal xi by a delayed decision φi−1100 of a decision unit 110. The decision φi100 is based on a reference phase ψi100 and the phase component θi100 described in more detail below. The rotation of the input signal xi is achieved by subtracting the output decision φi100 of the decision unit 110 from the phase component θi100 of the input signal xi.
A phase sum adder 112 performs the subtraction of the decision φi100 from the phase component θi100 in order to yield a rotated input phase ξi100. The rotated input phase ξi100 is input along with the amplitude Ai100 to a magnitude-and-phase-to-complex converter 114. The magnitude-and-phase-to-complex converter 114 outputs the reference signal ui100. The following equation holds true for the reference signal ui100:ui100=Ai100ej(θi100−φi100) i=1,2,3  (2)
The reference signal ui100 may remain disturbed by impairments such as noise and intersymbol interference (ISI). The impairments may be averaged out by integration at an integrator 108. The integrator 108 operates in the complex domain in order to ensure that the amplitude Ai100 of the semi-coherent demodulator 100 is considered. A coherency parameter α is input with the reference signal ui100 to form the output of the integrator 108, a reference vector ri100. Many approaches may be employed to integrate the reference signal ui100. In an embodiment of the invention, an exponential integration window yields the following equation:ri100=α*ri−1100+(1−α)*ui100 i=1,2,3  (3)The reference vector ri100 is input to a complex-to-phase converter 116. A reference phase ψi100 is output from the complex-to-phase converter 116 to a unit delay 118.
As noted above, in order to remove the impact of the modulation, a tentative decision is made at the decision unit 110 about a transmitted symbol of the input signal xi. The tentative decision is input to the phase sum adder 112. The decision φi100, which is made at the decision unit 110, is based upon a phase difference between the actual input phase component θi100 and a previous reference phase ψi−1100. The previous reference phase ψi−1100 is output from the unit delay 118. The unit delay 118 receives as an input the reference phase ψi100 from the complex-to-phase converter 116. The phase difference between the actual input phase component θi100 and the previous reference phase ψi−1100 is calculated by a second phase sum adder 120 and input to the decision unit 110.
The function of the decision unit 110 is dependent on the number of modulation levels M. For example, for M=2, the following equation is true:
                              φ          i          100                =                  {                                                    π                                                                                  if                    ⁢                                                                                                                  θ                          i                          100                                                -                                                  ψ                                                      i                            -                            1                                                    100                                                                                                                            ≥                                      π                    2                                                                                                      0                                            elsewhere                                              }                                    (        4        )            The decision φi100 is input to a second unit delay 122. A delayed decision φi−1100 output by the second unit delay 122 is then input to a phase sum adder 124 and a phase sum adder 126. The first additional phase sum adder 124 subtracts the delayed decision φi−1100 from the output of the phase sum adder 120. The output of the phase sum adder 124 is an output yi100 of the semi-coherent demodulator 100.
A previous phase difference θi−1100 is replaced with a corrected previous phase difference γi−1100. The corrected previous phase difference γi−1100 includes less noise than the previous phase difference θi−1100. The corrected previous phase difference γi−1100 is denoted by:γi−1100=ψi−1100+φi−1100 i=2,3  (5)The output yi100 of the semi-coherent demodulator 100, and thus also the output of phase sum adder 124, is given by the following equation:yi100=θi100−γi−1100 i=2,3  (6)
The phase sum adder 126 subtracts the delayed decision φi−1100 from the decision φi100 to produce a decision of the output D(yi100). The decision D(yi100) is input to a look-up table (LUT) 128 to output detected bits.
Calculations in both the phase and complex domains increase computational complexity. Phase-to-complex converters, complex-to-phase converters, integrators, etc. are needed to perform the necessary additional calculations. The additional computations result in excessive power consumption and silicon area in order to achieve the increased performance of the MDPSK semi-coherent demodulator 100.